Digital Blocks: Take the Technology, Take the World

The IP Core display controls are optimized for both Intel and Xilinx FPGAs, allowing the system designer to concentrate easily on the primary application, and not deal with display control challenges, to add a display to current or future FPGA designs. Furthermore, there is no need for an external display controller device, which would take up valuable PCB space and unnecessarily increase the project's BOM. 

Display Controller IP

 

Digital Blocks offers IP Core Controllers that contain a variety of optional features from basic baseline display requirements up to advanced display processing features. The Display Controller IP core perfectly fits the system specs thanks to its modular design and powerful scalability, without wasting any FPGA resources.

Some benefits of using Display Controller IP Core?

•       No external display controller is required that leads to a smaller PCB and a lower BOM.

•       Low resource use and excellent modular design scaling

•       The unified bus interface and the laid-out register bank provide for easy integration.

Multiple video inputs can be easily mixed and blended with the HMI thanks to the Display Controller IP core. Xilinx Base TRD shows the HMI blended over the processed video input that is the user-controlled level of transparency. Control IP Core Display IP Cores target ASIC/ FPGA's system application team in medical, industrial, aerospace or defense, automotive, computer, surveillance, and consumer applications. A detailed simulation test suite, Linux driver, Synopsys Design Constraints for synthesis, and a user manual are included with this IP core.

Basic Features & Performance of IP Core:

•       LVDS and HDMI/DVI display support without an external display controller device

•       Unlimited pages support for video

•       Integrated PWM generator for brightness control displays

•       2D accelerator unit optional (draw/copy rectangles, translucent color supports)

•       Color modes supported: real color 16-bit (5/6/5) and true color 24-bit

•       Up to 1280 × 1024 on low-cost FPGAs

•       Up to 1920 × 1080 on high-performance FPGAs

These special features will also facilitate the reuse for future projects of the Display Controller IP core. The selection of our display controller IP core for current or future projects would reduce both times to market and system costs dramatically. For more details, please check our official link here at https://www.digitalblocks.com/

 

Location: Glen Rock, NJ 07452, USA

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