AXI DMA: A Revolutionary Root takes the Global Future to Next Generation

AXI4 DMA Controller with Master AXI Interconnect provides 1-32 channels with a descriptor-driven CPU channel interface to control data transmission between memory subsystems or between memory and peripherals. It distinguishes between two channels: MM2S (memory-mapped to stream) transport data from DDR memory to FPGA and S2MM (stream to memory-mapped) transport arbitrary data stream to DDR memory.

 

Digital Blocks is a leading developer of Silicon-proven Intellectual Property cores for developers needing best-in-class IP for Embedded Processors, Multi-Channel Peripherals, Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines & many more.

 

What is the function of AXI 4 DMA?

 

●        The IP Core implements a highly efficient, configurable DMA engine specifically engineered for Artificial Intelligence optimized SoCs and FPGAs that power to virtualized data centers.

 

●        The DMA AXI IP is intended to be used as a centralized DMA allowing concurrent data movement in any direction and is particularly suited for many-core SoCs such as AI and ML processors.

 

●        The DMA AXI IP Core is based on a novel architecture that allows hundreds of independent and concurrent DMA channels to be distributed among a number of Virtual Machines or host domains without sacrificing performance and resource utilization.

 

●        The AXI4 DMA IP is optimized to deliver the highest possible throughput for small data packet transfers, which is a common weakness in traditional DMA engines. 

 

AXI4 DMA is transformed and supports many conventional systems and also produces over 10 times higher performance, more efficient bus power management, modern communication modes, and new applications. To know more details visit us at https://www.digitalblocks.com/

 

Location: Glen Rock, NJ 07452, USA

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