Digital Blocks Inc

The IP Core display controls are optimized for both Intel and Xilinx FPGAs, allowing the system designer to concentrate easily on the primary application, and not deal with display control challenges, to add a display to current or future FPGA designs. Furthermore, there is no need for an external display controller device, which would take up valuable PCB space and unnecessarily increase the project's BOM.    Digital Blocks offers IP Core Controllers that contain a variety of optional features from basic baseline display requirements up to advanced display processing features. The Display Controller IP core perfectly fits the system specs thanks to its modular design and powerful scalability, without wasting any FPGA resources . Some benefits of using Display Controller IP Core? •        No external display controller is required that leads to a smaller PCB and a lower BOM. •        Low resource use and ...

AXI4 DMA Controller with Master AXI Interconnect provides 1-32 channels with a descriptor-driven CPU channel interface to control data transmission between memory subsystems or between memory and peripherals. It distinguishes between two channels: MM2S (memory-mapped to stream) transport data from DDR memory to FPGA and S2MM (stream to memory-mapped) transport arbitrary data stream to DDR memory.   Digital Blocks is a leading developer of Silicon-proven Intellectual Property cores for developers needing best-in-class IP for Embedded Processors, Multi-Channel Peripherals, Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines & many more.   What is the function of AXI 4 DMA?   ●         The IP Core implements a highly efficient, configurable DMA engine specifically engineered for Artificial Intelligence optimized SoCs and FPGAs that power to virtualized data centers.   ...