AXI DMA Scatter Gather and Its Features
The direct memory access (DMA) controller grants a hardware subsystem to access the main memory with nominal supervision from the central processing unit (CPU). This reduces CPU workload when the system transmits vast amounts of memory multiple times. The DMA Controller core provides a system to transfer data between memory and AXI4-stream interface using direct mode or scatter-gather mode.
Characteristics
Memory interface in AXI4 full-duplex or AXI3 half-duplex
Programmable memory interface width
Control and status register with APB3 interface
Up to 8 channels of AXI4-stream interface
Programmable stream interface width
Enhance bandwidth with hardware read and write queue
Priority-weighted round-robin scheduling
Backups scatter-gather mode
Includes example design targeting the Trion® T120 BGA576 Development Board
AXI DMA Scatter Gather allows the application to specify a list of transactions in memory that the hardware will action without more application interference. During this time, the application can add more work to keep the Hardware busy.
User can confirm the completion of transactions through polling the hardware, or interrupts. AXI DMA Scatter Gather processes complete packets. A packet refers a series of data bytes that represent a message. AXI DMA Scatter Gather allows a packet of data to be scattered into one or more transactions. For instance, take an Ethernet IP packet that comprises of a 14 byte header followed by a 1 or more bytes of payload. With SGDMA, the application may point a BD to the header and another BD to the payload, and then transmit them as a single message. This tactic can make a TCP/IP stack well-organized by allowing it to keep packet header and data in separate memory regions instead of gathering packets into the closest blocks of memory.
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