Master/Slave controller IP Processor | Digital Blocks Inc
Digital Blocks offers complete I 2C IP Verilog Cores protocol & timing compliant with Master / Slave, Master-only and Slave-only functions . The I2C interface can hold the I2C bus by holding the sclk line low until the host provides more data to enable the transfer to proceed, or until the host allows termination of the transfer. If the host doesn't enable bus hold function, the device should terminate the connection while it serves as master. The Master / Slave I2C Controller IP Cores (Verilog Cores DB-I2C-MS-APB, DB-I2C-MS-AHB, DB-I2C-MS-AXI, DB-I2C-MS-AVLN) are fitted with a parameterized FIFO, Control Panel, & Interrupt Handler to completely offload the processor I2C Switch. The complete off-load capabilities aim systems with the specifications of low performing algorithms or limited software development plans. Digital Blocks provides I2C Controller IP Core reference designs and tests that enable you to accelerate the I2C Bus configuration within your device. ...